VibeGDS plain-English photonic layout VibeASIC →
connecting

Describe a photonic device. I write the gdsfactory script, run it, check design rules, and draw the layout. Ask for changes in plain English.

Try: "an add-drop ring resonator, radius 12 um, gap 0.2 um" or pick an example. Choose a fab in the top bar to design against that foundry's real cells, layers and rules, or an ASIC process to design a digital chip.

VibeASIC: describe a digital chip. I write the Verilog, then the server runs the full OpenROAD flow on the open PDK you picked: synthesis, floorplan, placement, clock tree, routing, GDS. You get the real layout, timing, area and power.

Try: "an 8-bit counter with enable" or "a UART transmitter at 115200 baud from 10 MHz". A small block takes a few minutes; nothing runs on your machine.

x 0.000 y 0.000 µm

No layout yet

gdsfactory script · edit and run

Circuit-level S-parameters from the layout netlist (SAX, analytic models). Good for MZIs, rings, splitters, couplers. Not a full-wave solver.

Static timing, area and power from the OpenROAD flow appear after a build.

Flow checks: router DRC, antenna, timing. The KLayout deck is the PDK's own rule file.

Design-rule results appear after a build.

Ports, netlist and lengths appear after a build.

Pick a fab in the top bar, then prepare a submission: the design is placed in the fab's design area with a floorplan and label, checked against the fab's published rules, and exported as the top cell the fab expects.

Shuttle options and the submission checklist for the chosen process appear here.