VibeGDS plain-English photonic layout
connecting Store ↗ VibeQ ↗ VibeASIC ↗

Describe a photonic device. I write the VibeGDS script, run it, check design rules, and draw the layout. Ask for changes in plain English.

Try: "an add-drop ring resonator, radius 12 um, gap 0.2 um" or pick an example. Choose a fab in the top bar to design against that foundry's real cells, layers and rules, or an ASIC process to design a digital chip.

VibeASIC: describe a digital chip. I write the Verilog, then the server runs the full OpenROAD flow on the open PDK you picked: synthesis, floorplan, placement, clock tree, routing, GDS. You get the real layout, timing, area and power.

Try: "an 8-bit counter with enable" or "a UART transmitter at 115200 baud from 10 MHz". A small block takes a few minutes; nothing runs on your machine.

Describe the chip, or a change to it
x 0.000 y 0.000 µm

No layout yet

Waiting for draft chip to be ready…
VibeGDS script · edit and run
Waiting for draft chip to be ready…

Circuit-level S-parameters from the layout netlist (SAX, analytic models). Good for MZIs, rings, splitters, couplers. Not a full-wave solver.

Simulation results, static timing, area and power appear after a build.

Flow checks: router DRC, antenna, timing. The KLayout deck is the PDK's own rule file; LVS compares layout with netlist.

Design-rule results appear after a build.

Ports, netlist and lengths appear after a build.

SPICE netlist co-simulated with the layout · heaters (H), modulators (M), photodiodes (D)

Ask for drive electronics in the chat (a heater with a voltage, a modulator, a photodiode into a load) or write the netlist here. Each step of the co-simulation is checked and reported.

After the fab: Store ↗

Pick a fab in the top bar, then prepare a submission: the design is placed in the fab's design area with a floorplan and label, checked against the fab's published rules, and exported as the top cell the fab expects. Dies come back bare and untested: the Store lists the alignment rig, laser and power meter, or the labs that measure dies for you.

Shuttles and the submission checklist for the chosen process.After the fab: Store ↗

Shuttle options and the submission checklist for the chosen process appear here. When the chip comes back, the Store lists the board, the driver and the bench instruments that test it.